Invention Grant
- Patent Title: Multi-chip-module semiconductor chip package having dense package wiring
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Application No.: US14655688Application Date: 2014-07-28
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Publication No.: US10256211B2Publication Date: 2019-04-09
- Inventor: Chuan Hu , Chia-Pin Chiu , Johanna Swan
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- International Application: PCT/US2014/048510 WO 20140728
- International Announcement: WO2016/018237 WO 20160204
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L25/00 ; H01L23/31 ; H01L21/56 ; H01L23/538 ; H01L21/48 ; H01L23/498
Abstract:
An apparatus is described having a build-up layer. The build-up layer has a pad side of multiple die pressed into a bottom side of the build-up layer. The multiple die have wide pads to facilitate on wafer testing of the multiple die. The wide pads are spaced a minimum distance permitted by a manufacturing process used to manufacture their respective die. The build-up layer above the wide pads is removed. The apparatus also includes metallization on a top side of the build-up layer that substantially fills regions above the wide pads. The metallization includes lands above the wide pads and multiple wires between the wide pads.
Public/Granted literature
- US20160293578A1 MULTI-CHIP-MODULE SEMICONDUCTOR CHIP PACKAGE HAVING DENSE PACKAGE WIRING Public/Granted day:2016-10-06
Information query
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