Invention Grant
- Patent Title: Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory
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Application No.: US14865617Application Date: 2015-09-25
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Publication No.: US10261901B2Publication Date: 2019-04-16
- Inventor: Zhe Wang , Christopher B. Wilkerson , Zeshan A. Chishti , Seth H. Pugsley , Alaa R. Alameldeen , Shih-Lien L. Lu
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0811 ; G06F3/06 ; G06F12/0862 ; G06F12/0888 ; G06F12/0893 ; G06F13/00 ; G06F13/28
Abstract:
An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.
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