Invention Grant
- Patent Title: Method for a stage optimized high speed adder
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Application No.: US15659393Application Date: 2017-07-25
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Publication No.: US10282170B2Publication Date: 2019-05-07
- Inventor: Mohammad Abdallah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: NDWE, LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F7/504 ; H04L12/66
Abstract:
A method for fast parallel adder processing. The method includes receiving parallel inputs from a communications path, wherein each input comprises one bit, adding the inputs using a parallel structure, wherein the parallel structure is optimized to accelerate the addition by utilizing a characteristic that the inputs are one bit each, and transmitting the resulting outputs to a subsequent stage.
Public/Granted literature
- US20170322772A1 METHOD FOR A STAGE OPTIMIZED HIGH SPEED ADDER Public/Granted day:2017-11-09
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