公开(公告)号：US09934042B2

公开(公告)日：2018-04-03

申请号：US14216859

申请日：2014-03-17

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/30094 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838

Abstract: A method for dependency broadcasting through a block organized source view data structure. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating a block organized source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks as recorded by the plurality of register templates; upon dispatch of one block of the instruction blocks, broadcasting a number belonging to the one block to a column of the source view data structure that relates that block and marking the column accordingly; and updating the dependency information of remaining instruction blocks in accordance with the broadcast.

公开(公告)号：US09921850B2

公开(公告)日：2018-03-20

申请号：US15353623

申请日：2016-11-16

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30058 ,  G06F9/3808 ,  G06F9/3844

Abstract: A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer.

公开(公告)号：US20180011738A1

公开(公告)日：2018-01-11

申请号：US15712017

申请日：2017-09-21

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/52 ,  G06F9/30

CPC classification number: G06F9/4881 ,  G06F9/30094 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/48 ,  G06F9/4887 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5027 ,  G06F9/5038 ,  G06F9/52 ,  G06F9/524

Abstract: A method for executing multithreaded instructions grouped into blocks. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein the instructions of the instruction blocks are interleaved with multiple threads; scheduling the instructions of the instruction block to execute in accordance with the multiple threads; and tracking execution of the multiple threads to enforce fairness in an execution pipeline.

公开(公告)号：US09811342B2

公开(公告)日：2017-11-07

申请号：US14213218

申请日：2014-03-14

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3836 ,  G06F9/3853

Abstract: A method for executing dual dispatch of blocks and half blocks. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and performing a dual dispatch of the two half blocks for execution on an execution unit.

公开(公告)号：US09720839B2

公开(公告)日：2017-08-01

申请号：US14922035

申请日：2015-10-23

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08 ,  G06F12/0846 ,  G06F12/0895

CPC classification number: G06F12/0846 ,  G06F12/0848 ,  G06F12/0895 ,  G06F2212/1021 ,  G06F2212/6082

Abstract: Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data.

公开(公告)号：US09720831B2

公开(公告)日：2017-08-01

申请号：US14922042

申请日：2015-10-23

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/0897 ,  G06F12/12

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/283 ,  G06F2212/608

Abstract: A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.

公开(公告)号：US20170161074A1

公开(公告)日：2017-06-08

申请号：US14961464

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/30174 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/3808 ,  G06F9/3836 ,  G06F9/3863 ,  G06F9/4552 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method for translating instructions for a processor. The method includes accessing a guest instruction and performing a first level translation of the guest instruction using a first level conversion table. The method further includes outputting a resulting native instruction when the first level translation proceeds to completion. A second level translation of the guest instruction is performed using a second level conversion table when the first level translation does not proceed to completion, wherein the second level translation further processes the guest instruction based upon a partial translation from the first level conversion table. The resulting native instruction is output when the second level translation proceeds to completion.

公开(公告)号：US11281481B2

公开(公告)日：2022-03-22

申请号：US14806169

申请日：2015-07-22

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/455 ,  G06F8/41

Abstract: A system for an agnostic runtime architecture is disclosed. The system includes a system emulation/virtualization converter, an application code converter, and a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image. The system converter further comprises a guest fetch logic component for accessing a plurality of guest instructions, a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling the plurality of guest instructions into a guest instruction block, and a plurality of conversion tables including a first level conversion table and a second level conversion table coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The system further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache, and in response to the hit the conversion look aside buffer forwards the translated native instruction for execution.

公开(公告)号：US11003459B2

公开(公告)日：2021-05-11

申请号：US16383212

申请日：2019-04-12

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/38 ,  H04L12/28 ,  G06F12/00 ,  G06F9/46 ,  G06F15/173 ,  G06F9/30 ,  G06F13/00 ,  H04L12/933 ,  G06F12/0886 ,  G06F12/0853

Abstract: A method and apparatus including a cache controller coupled to a cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage of the cache controller to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs the combining and splitting of the plurality of cache access request by a second stage of the cache controller, and applies the plurality of cache access requests to the cache memory at line speed.

公开(公告)号：US10372454B2

公开(公告)日：2019-08-06

申请号：US15354742

申请日：2016-11-17

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F13/16 ,  G06F13/40

Abstract: A method for allocation of a segmented interconnect in an integrate circuit is disclosed. The method comprises receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences. The method also comprises contending for the plurality of resources in accordance with requests from the plurality of resource consumers. Finally, the method comprises accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of global segment buses.