Invention Grant
- Patent Title: Page faulting and selective preemption
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Application No.: US15482808Application Date: 2017-04-09
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Publication No.: US10282812B2Publication Date: 2019-05-07
- Inventor: Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLC
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F9/46 ; G06F9/48 ; G06T1/20

Abstract:
One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
Public/Granted literature
- US20180293692A1 PAGE FAULTING AND SELECTIVE PREEMPTION Public/Granted day:2018-10-11
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