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公开(公告)号：US20230260195A1
公开(公告)日：2023-08-17
申请号：US18165842
申请日：2023-02-07
Applicant: Intel Corporation
Inventor： Ingo Wald
CPC classification number: G06T15/06 , G06T1/20 , G06T15/005
Abstract: An apparatus and method are described for utilizing volume proxies. For example, one embodiment of an apparatus comprises: a volume subdivision module to subdivide a volume into a plurality of partitions, the apparatus to process a first of the partitions and to distribute data associated with each of the other partitions to each of a plurality of nodes; a proxy generation module to compute a first proxy for the first partition, the first proxy to be transmitted to the plurality of nodes; and a ray tracing engine to perform one or more traversal/intersection operations for a current ray or group of rays using the first proxy; if the ray or group of rays interacts with the first proxy, then the ray tracing engine to send the ray(s) to a second node associated with the first proxy or retrieves data related to the interaction from the second node.
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公开(公告)号：US11657472B2
公开(公告)日：2023-05-23
申请号：US17707118
申请日：2022-03-29
Applicant: INTEL CORPORATION
Inventor： Carsten Benthin , Sven Woop , Ingo Wald
CPC classification number: G06T1/20 , G06F9/3877 , G06T15/005 , G06T15/06 , G06T17/10 , G06T2210/12
Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.
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公开(公告)号：US11321902B2
公开(公告)日：2022-05-03
申请号：US16804379
申请日：2020-02-28
Applicant: INTEL CORPORATION
Inventor： Tomas G. Akenine-Moller , Ingo Wald
Abstract: An apparatus and method for efficient ray tracing. For example, one embodiment of an apparatus comprises: a general purpose processor to generate a plurality of ray streams; a first hardware queue to receive the ray streams generated by the general purpose processor; a graphics processing unit (GPU) comprising a plurality of execution units (EUs) to process the ray streams from the first hardware queue; a second hardware queue to store graphics processing jobs submitted by the GPU; the general purpose processor to process the jobs submitted by the GPU and share results with the GPU.
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公开(公告)号：US10649524B2
公开(公告)日：2020-05-12
申请号：US15482694
申请日：2017-04-07
Applicant: Intel Corporation
Inventor： Ingo Wald , Brent E. Insko , Prasoonkumar Surti , Adam T. Lake , Peter L. Doyle , Daniel Pohl
Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.
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公开(公告)号：US10395423B2
公开(公告)日：2019-08-27
申请号：US15394786
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Ingo Wald
Abstract: An apparatus and method are described for rendering adaptive mesh refinement data. For example, one embodiment of a graphics processing apparatus comprises: a tree data structure generator to transform adaptive mesh refinement (AMR) data into a multi-octree or kd-tree data structure, respectively; an interpolator to implement an interpolation scheme based on the multi-octree or kd-tree data structure to generate interpolated results, the interpolation scheme using repeated linear interpolation; and a ray tracing-based renderer to use the interpolated results to render image frames using ray tracing techniques.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20180300841A1
公开(公告)日：2018-10-18
申请号：US15488842
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Altug Koker , Jacek Kwiatkowski , Ingo Wald , Jefferson Amstutz , Johannes Guenther , Gabor Liktor , Elmoustapha Ould-Ahmed-Vall
Abstract: Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment.
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公开(公告)号：US20180293692A1
公开(公告)日：2018-10-11
申请号：US15482808
申请日：2017-04-09
Applicant: Intel Corporation
Inventor： Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
CPC classification number: G06T1/20 , G06F9/3009 , G06F9/30185 , G06F9/3851 , G06F9/461 , G06F9/4843
Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
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8.发明申请公开(公告)号：US20170249781A1
公开(公告)日：2017-08-31
申请号：US15053693
申请日：2016-02-25
Applicant: Intel Corporation
Inventor： Ingo Wald
CPC classification number: G06T17/005 , G06T1/20 , G06T15/005
Abstract: Embodiments provide for a graphics processing apparatus including logic to receive data from an input buffer. The data can define a set of data points, where each data point includes one or more dimensions. The logic is configured to process the received data points to perform in-place construct a left-balanced and complete point k-d tree of the data points within the input buffer.
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公开(公告)号：US20250095099A1
公开(公告)日：2025-03-20
申请号：US18893028
申请日：2024-09-23
Applicant: Intel Corporation
Inventor： Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
Abstract: One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.
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10.发明授权公开(公告)号：US12175589B2
公开(公告)日：2024-12-24
申请号：US18228777
申请日：2023-08-01
Applicant: INTEL CORPORATION
Inventor： Ingo Wald , Carsten Benthin , Sven Woop
Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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