Invention Grant
- Patent Title: Integrated circuit layout structure
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Application No.: US15466871Application Date: 2017-03-23
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Publication No.: US10290653B2Publication Date: 2019-05-14
- Inventor: Chien-Hung Chen , Chun-Hsien Wu
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: TW103132848A 20140923
- Main IPC: H01L27/118
- IPC: H01L27/118 ; H01L27/02 ; H01L27/092

Abstract:
An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes one first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type. And an area of the first doped region is smaller than an area of the total second doped regions.
Public/Granted literature
- US20170194349A1 INTEGRATED CIRCUIT LAYOUT STRUCTURE Public/Granted day:2017-07-06
Information query
IPC分类: