公开(公告)号：US09898569B2

公开(公告)日：2018-02-20

申请号：US14852635

申请日：2015-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Wu ,  Chen-Hsien Hsu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chien-Hung Chen

IPC: H01L21/70 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.

公开(公告)号：US20170194349A1

公开(公告)日：2017-07-06

申请号：US15466871

申请日：2017-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Chun-Hsien Wu

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11885

Abstract: An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes one first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type. And an area of the first doped region is smaller than an area of the total second doped regions.

公开(公告)号：US10290653B2

公开(公告)日：2019-05-14

申请号：US15466871

申请日：2017-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Chun-Hsien Wu

IPC: H01L27/118 ,  H01L27/02 ,  H01L27/092

Abstract: An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes one first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type. And an area of the first doped region is smaller than an area of the total second doped regions.

公开(公告)号：US20160086932A1

公开(公告)日：2016-03-24

申请号：US14526536

申请日：2014-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Chun-Hsien Wu

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11885

Abstract: An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes at least one or more first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type.

Abstract translation: 具有双高度标准单元的集成电路布局结构包括至少包括第一单元高度的第一标准单元和至少包括第二单元高度的第二标准单元。 第二个单元格高度是第一个单元格高度的一半。 第一标准单元包括在第一标准单元的中间形成的至少一个或多个第一掺杂区和形成在第一标准单元的顶侧和底侧的多个第二掺杂区。 第一掺杂区域包括第一导电类型，第二掺杂区域包括与第一导电类型互补的第二导电类型。

公开(公告)号：US20170039311A1

公开(公告)日：2017-02-09

申请号：US14852635

申请日：2015-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Wu ,  Chen-Hsien Hsu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chien-Hung Chen

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.

Abstract translation: 一种用于设计半导体布局结构的方法包括以下步骤。 接收包括至少第一活动特征的第一活动特征组，并且第一活动特征包括第一信道长度。 引入一对第一虚拟特征以形成第一细胞图案。 第一虚拟特征包括第一虚拟宽度。 在第一活动特征组和第一虚拟特征之一之间限定第一间隔宽度，并且在第一活动特征组和第二虚拟特征之间限定第三间隔宽度。 第一单元图案包括第一单元宽度和第一多段间距，并且第一单元宽度是第一间距的倍数。 至少由计算机辅助设计工具执行第一活动特征组的接收和第一虚拟特征的引入。