Invention Grant
- Patent Title: Tapered vertical FET having III-V channel
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Application No.: US15658746Application Date: 2017-07-25
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Publication No.: US10297686B2Publication Date: 2019-05-21
- Inventor: Karthik Balakrishnan , Kangguo Cheng , Pouya Hashemi , Alexander Reznicek
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78 ; H01L21/02 ; H01L29/08 ; H01L29/20 ; H01L29/10 ; H01L29/423 ; H01L29/66
Abstract:
A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.
Public/Granted literature
- US20180053845A1 TAPERED VERTICAL FET HAVING III-V CHANNEL Public/Granted day:2018-02-22
Information query
IPC分类:
