Invention Grant
- Patent Title: I/O layout footprint for multiple 1LM/2LM configurations
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Application No.: US15640148Application Date: 2017-06-30
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Publication No.: US10304814B2Publication Date: 2019-05-28
- Inventor: Konika Ganguly , Robert J. Royer, Jr. , Rebecca Z. Loop , Anthony M. Constantine , Bilal Khalaf
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G11C14/00
- IPC: G11C14/00 ; H01L23/50 ; H01L25/18 ; H01L23/498

Abstract:
An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower package. One of the packages contain memory devices of a first type and the other of the packages contain memory devices of a second type. I/O connections on the underside of the upper package's substrate are vertically aligned with their corresponding, first I/O connections on the underside of the lower package's substrate. The first I/O connections are located outside second I/O connections on the underside of the lower package's substrate for the lower package.
Public/Granted literature
- US20190006340A1 I/O Layout Footprint For Multiple 1LM/2LM Configurations Public/Granted day:2019-01-03
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