公开(公告)号：US12040568B2

公开(公告)日：2024-07-16

申请号：US17128803

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Xiang Li ,  Konika Ganguly ,  George Vergis

IPC: H01R13/6461 ,  H01R12/70 ,  H01R12/71 ,  H01R13/24

CPC classification number: H01R12/7076 ,  H01R12/7082 ,  H01R12/714 ,  H01R13/2435

Abstract: Connectors with a staggered pin orientation can reduce crosstalk amongst signal pins. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. Each of the plurality of pins includes two ends including a card or module-facing end to couple with the card or module and a motherboard-facing end to couple with the motherboard. Each of the plurality of pins includes a middle section in the connector housing. One or both of the ends include one or more bends relative to the middle section. The plurality of pins includes alternating signal pins and ground pins, wherein the signal pins having an opposite orientation relative to the ground pins.

公开(公告)号：US12294167B2

公开(公告)日：2025-05-06

申请号：US17375558

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Xiang Li ,  Konika Ganguly ,  George Vergis

IPC: H01R12/71 ,  H01R12/70

Abstract: A connector includes connector pins that have a loop of conductor. The connector connects a first printed circuit board (PCB) to a second PCB with compression of the connector pins between the two boards. In response to compression of the connector, the connector pins make electrical contact with themselves through the loop, while also connecting pads of the first PCB to pads of the second PCB.

公开(公告)号：US10467160B2

公开(公告)日：2019-11-05

申请号：US15719742

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Xiang Li ,  Yunhui Chu ,  Jun Liao ,  George Vergis ,  James A. McCall ,  Charles C. Phares ,  Konika Ganguly ,  Qin Li

IPC: G11C5/02 ,  G06F13/16 ,  G11C5/06 ,  G06F1/18 ,  H01R12/73 ,  G11C5/04 ,  G11C7/10

Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.

公开(公告)号：US12300918B2

公开(公告)日：2025-05-13

申请号：US17479596

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Navneet Kumar Singh ,  Aiswarya M. Pious ,  Richard S. Perry ,  Amarjeet Kumar ,  Siva Prasad Jangili Ganga ,  Gaurav Hada ,  Sushil Padmanabhan ,  Konika Ganguly

IPC: H01R12/00 ,  H01R12/70 ,  H01R12/73 ,  H01R43/26

Abstract: A connector to connect an electronic module to an edge of a first electronic circuit board is described. The module has a second electronic circuit board. The connector has a top part that houses a first row of I/Os. The top part is to be placed on a surface of the first electronic circuit board. The connector has a bottom part that houses a second row of I/Os. The bottom part is to be placed on an opposite surface of the first electronic circuit board, wherein, the top and bottom parts form inner and outer stand-offs when mater together. The inner stand-off is to reside within a through hole of the first electronic circuit board. The outer stand-off is to reside within free space off the edge of the first electronic circuit board. The second electronic circuit board is to be pressed in between the first row of I/Os and the second row of I/Os when the module is connected to the connector.

公开(公告)号：US12106818B2

公开(公告)日：2024-10-01

申请号：US17133484

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Aiswarya M. Pious ,  Raji James ,  Phani K. Alaparthi ,  George Vergis ,  Bill Nale ,  Konika Ganguly

IPC: G11C5/14 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3296 ,  G11C11/4074

CPC classification number: G11C5/148 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3296 ,  G11C5/141 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.

公开(公告)号：US11295998B2

公开(公告)日：2022-04-05

申请号：US15945641

申请日：2018-04-04

Applicant: Intel Corporation

Inventor： Stephen Christianson ,  Stephen Hall ,  Emile Davies-Venn ,  Dong-Ho Han ,  Kemal Aygun ,  Konika Ganguly ,  Jun Liao ,  M. Reza Zamani ,  Cory Mason ,  Kirankumar Kamisetty

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01P3/08 ,  H01L21/48 ,  H01P11/00

Abstract: Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.

公开(公告)号：US10304814B2

公开(公告)日：2019-05-28

申请号：US15640148

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Konika Ganguly ,  Robert J. Royer, Jr. ,  Rebecca Z. Loop ,  Anthony M. Constantine ,  Bilal Khalaf

IPC: G11C14/00 ,  H01L23/50 ,  H01L25/18 ,  H01L23/498

Abstract: An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower package. One of the packages contain memory devices of a first type and the other of the packages contain memory devices of a second type. I/O connections on the underside of the upper package's substrate are vertically aligned with their corresponding, first I/O connections on the underside of the lower package's substrate. The first I/O connections are located outside second I/O connections on the underside of the lower package's substrate for the lower package.

公开(公告)号：US20220353991A1

公开(公告)日：2022-11-03

申请号：US17866775

申请日：2022-07-18

Applicant: Intel Corporation

Inventor： Xiang Li ,  Konika Ganguly ,  George Vergis ,  Stephen Christianson ,  Xiaopeng Dong

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/14

Abstract: An example of an apparatus may comprise a first set of compression contact pads formed on a first side of a circuit board, a second set of compression contact pads formed on a second side of the circuit board opposite to the first side of the circuit board, where the first set of compression contact pads are respectively electrically connected to the second set of compression pads. An example of the circuit board may include a memory board. An example stackable memory module may include memory devices mounted to both sides of the memory board. Other examples are disclosed and claimed.

公开(公告)号：US20220217846A1

公开(公告)日：2022-07-07

申请号：US17700972

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Xiang Li ,  Konika Ganguly ,  George Vergis ,  Stephen Christianson ,  Xiaopeng Dong ,  Landon Hanks

IPC: H05K1/14 ,  H05K1/11 ,  H05K1/18

Abstract: An embodiment of an electronic apparatus comprises a circuit board, one or more memory devices affixed to a top side of the circuit board, and one or more board-to-board connectors affixed to a bottom side of the circuit board to provide an external connection to signals of the one or more memory devices, where the one or more board-to-board connectors are located inward from outermost edges of the circuit board and where a first footprint defined by an outermost boundary of the one or more board-to-board connectors is substantially a same size as or smaller than a second footprint defined by an outermost boundary of the one or more memory devices. Other embodiments are disclosed and claimed.