An apparatus includes a receiver circuit and a data buffer. The receiver circuit may comprise a decision feedback equalizer (DFE). The data buffer circuit may be configured to initialize a condition of the receiver circuit in response to a control signal prior to reception of a command sequence associated with a directed access to a memory system. The control signal generally indicates detection of a non-consecutive clock associated with a start of the command sequence. The data buffer circuit may generate one or more tap enable signals configured to determine a number of clock cycles during which a contribution of one or more taps of the decision feedback equalizer (DFE) are delayed.