Invention Grant
- Patent Title: Hardmask layer for 3D NAND staircase structure in semiconductor applications
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Application No.: US15175880Application Date: 2016-06-07
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Publication No.: US10312137B2Publication Date: 2019-06-04
- Inventor: Eswaranand Venkatasubramanian , Susmit Singha Roy , Pramit Manna , Abhijit Basu Mallick
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/768 ; H01L23/522 ; H01L23/528 ; H01L27/1157 ; H01L27/11524 ; H01L27/11556 ; H01L27/11582

Abstract:
Embodiments of the present disclosure provide an apparatus and methods for forming a hardmask layer that may be utilized to transfer patterns or features to a film stack with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked semiconductor devices. In one embodiment, a method of forming a hardmask layer on a substrate includes forming a seed layer comprising boron on a film stack disposed on a substrate by supplying a seed layer gas mixture in a processing chamber, forming a transition layer comprising born and tungsten on the seed layer by supplying a transition layer gas mixture in the processing chamber, and forming a bulk hardmask layer on the transition layer by supplying a main deposition gas mixture in the processing chamber.
Public/Granted literature
- US20170352586A1 HARDMASK LAYER FOR 3D NAND STAIRCASE STRUCTURE IN SEMICONDUCTOR APPLICATIONS Public/Granted day:2017-12-07
Information query
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