Invention Grant
- Patent Title: End to end FPGA diagnostics for a safety system
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Application No.: US15456034Application Date: 2017-03-10
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Publication No.: US10338995B2Publication Date: 2019-07-02
- Inventor: Gary Perkins , Malcolm J. Rush , Martin Peter John Cornes , Andrew Porter , Rajesh Mangal
- Applicant: Artesyn Embedded Computing, Inc.
- Applicant Address: US AZ Tempe
- Assignee: Artesyn Embedded Computing, Inc.
- Current Assignee: Artesyn Embedded Computing, Inc.
- Current Assignee Address: US AZ Tempe
- Agency: Harness, Dickey & Pierce, P.L.C.
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07 ; G06F11/16 ; G06F11/30 ; G06F11/20

Abstract:
A system includes a first fail-safe chassis (FSC) receives module health signals from a plurality of modules and generates a first chassis health signal. The chassis health signal includes first and second portions. A plurality of modules receives the chassis health signal. The FSC determines whether one or more of the module heals signals indicates an associated module is unhealthy by comparing the module health signals and a predetermined health value. The FSC selectively de-asserts the first chassis health signal based on the comparison. A second FSC operates similarly. A safety relay box determines the health of the system in accordance with the first and second chassis health signals.
Public/Granted literature
- US20180260272A1 End To End FPGA Diagnostics For A Safety System Public/Granted day:2018-09-13
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