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    Integrated Thermal Inserts and Cold Plate
    2.
    发明申请
    Integrated Thermal Inserts and Cold Plate 审中-公开

    公开(公告)号：US20170273219A1

    公开(公告)日：2017-09-21

    申请号：US15616257

    申请日：2017-06-07

    Applicant: Artesyn Embedded Computing, Inc.

    Inventor： Suzanne Marye WONG ,  Martin Peter John CORNES ,  Robert Charles TUFFORD

    IPC: H05K7/20

    CPC classification number: H05K7/20545

    Abstract: A cooling system having integrated cold plate extending member and cold plate for an electronics enclosure includes a chassis having multiple heat producing boards positioned in side-by-side parallel configuration having successive ones of the boards separated by a cavity thereby defining multiple ones of the cavities. A cold plate assembly includes a base unit of a thermally conductive material. The cold plate assembly also includes multiple cold plate extending members connected to the base unit. Successive ones of the cold plate extending members are spaced to be slidably received in one of the cavities such that the cold plate extending member received between any two successive boards is in direct contact with both of the successive ones of the boards.

    Fault-tolerant failsafe computer system using COTS components
    3.
    发明授权
    Fault-tolerant failsafe computer system using COTS components 有权

    公开(公告)号：US09665447B2

    公开(公告)日：2017-05-30

    申请号：US14140686

    申请日：2013-12-26

    Applicant: Artesyn Embedded Computing, Inc.

    Inventor： Martin Peter John Cornes ,  Pasi Jukka Petteri Vaananen ,  Liu Jiang

    IPC: G06F11/00 ,  G06F11/16

    CPC classification number: G06F11/1637 ,  G06F11/165

    Abstract: A system includes a safety relevant component that generates a data packet in response to receiving a request to perform a task and that communicates the data packet. The system further includes a first fail-safe chassis (FSC) that continuously generates a first chassis health signal, that determines whether the data packet is valid, and that selectively determines whether to de-assert the first chassis health signal based on the determination. The system also includes a second FSC that continuously generates a second chassis health signal, that determines whether a copy of the data packet is valid, and that selectively determines whether to de-assert the second chassis health signal based on the determination. The system further includes a safety relay box module that determines whether to instruct the first FSC to operate in a predetermined mode based on the first chassis health signal and the second chassis health signal.

    Task based voting for fault-tolerant fail safe computer systems
    4.
    发明授权
    Task based voting for fault-tolerant fail safe computer systems 有权
    基于任务的容错故障安全计算机系统投票

    公开(公告)号：US09311212B2

    公开(公告)日：2016-04-12

    申请号：US14141594

    申请日：2013-12-27

    Applicant: Artesyn Embedded Computing, Inc.

    Inventor： Pasi Jukka Petteri Vaananen ,  Martin Peter John Cornes ,  Liu Jiang

    IPC: G06F11/00 ,  G06F11/34

    CPC classification number: G06F11/3409 ,  G06F11/1633 ,  G06F11/165

    Abstract: A system includes a first application that writes a first plurality of tasks to a first memory buffer; a second memory buffer that receives a copy of the first plurality of tasks; a second application that writes a second plurality of tasks to a third memory buffer; and a fourth memory buffer that receives a copy of the second plurality of tasks. The system further includes a first comparison module that generates a first voting signal based on a first comparison between a first task and a second task. The system further includes a second comparison module that generates a second voting signal based on a second comparison between the first task and the second task. The system further includes a first central processing unit (CPU) that selectively determines whether to de-assert a module health signal based on the first voting signal and the second voting signal.

    Abstract translation: 系统包括将第一多个任务写入第一存储器缓冲器的第一应用程序; 第二存储器缓冲器，其接收所述第一多个任务的副本; 将第二多个任务写入第三存储器缓冲器的第二应用程序; 以及第四存储器缓冲器，其接收第二多个任务的副本。 该系统还包括第一比较模块，其基于第一任务和第二任务之间的第一比较来生成第一投票信号。 该系统还包括第二比较模块，其基于第一任务和第二任务之间的第二比较来生成第二投票信号。 该系统还包括第一中央处理单元（CPU），其基于第一投票信号和第二投票信号选择性地确定是否去除模块健康信号。

    Thermal Conduction To A Cylindrical Shaft
    5.
    发明申请
    Thermal Conduction To A Cylindrical Shaft 审中-公开
    圆柱轴的导热

    公开(公告)号：US20160088776A1

    公开(公告)日：2016-03-24

    申请号：US14490186

    申请日：2014-09-18

    Applicant: Artesyn Embedded Computing, Inc.

    Inventor： Martin Peter John CORNES ,  Suzanne Marye WONG ,  Ross L. ARMSTRONG ,  Douglas L. SANDY

    IPC: H05K7/20

    CPC classification number: H05K7/2039

    Abstract: A canister system having a cylindrical housing and a modular electronic rack system disposed within the cylindrical housing. The modular electronic rack system includes a thermal contact member that is in at least selective physical contact with an interior surface of the cylindrical housing to permit conductive heat transfer there through. An input/output device extends along at least a portion of the modular electronic rack system and includes a power input and a signal output electrically coupled thereto. A plurality of electronic slots disposed at a position generally along the modular electronic rack system is provided.

    Abstract translation: 一种具有圆柱形壳体和设置在圆柱形壳体内的模块化电子架系统的罐系统。 模块化电子机架系统包括热接触构件，该热接触构件至少与圆柱形壳体的内表面选择性物理接触，以允许通过其导电传热。 输入/输出装置沿着模块化电子机架系统的至少一部分延伸，并且包括电力输入和与其电耦合的信号输出。 设置在大致沿着模块化电子机架系统的位置处的多个电子槽。

    FPGA mismatched packet stop for a safety system
    6.
    发明授权
    FPGA mismatched packet stop for a safety system 有权

    公开(公告)号：US10372579B2

    公开(公告)日：2019-08-06

    申请号：US15455619

    申请日：2017-03-10

    Applicant: Artesyn Embedded Computing, Inc.

    Inventor： Gary Perkins ,  Malcolm J. Rush ,  Andrew Porter

    IPC: G06F11/00 ,  G06F11/34 ,  H04L29/06 ,  G06F11/30 ,  G06F11/07 ,  G06F11/277 ,  H04L29/08 ,  H04L29/14

    Abstract: A fault-tolerant failsafe computer voting system including a first voting module that generates a first key based on a comparison between a first data packet and a copy of a second data packet. The first voting module determines whether the first key and a second key are valid keys. The second data packet is a copy of the first data packet. A second voting module generates the second key based on a comparison between the second data packet and a copy of the first data packet. A processing module generates an outgoing data packet based on the first data packet in response to determining whether the first key and the second key are valid keys. The first voting module is inhibited from generating the second key and the second voting module is inhibited from generating the first key.

    Method and system of synchronizing processors to the same computational point
    8.
    发明授权
    Method and system of synchronizing processors to the same computational point 有权

    公开(公告)号：US10042812B2

    公开(公告)日：2018-08-07

    申请号：US15148271

    申请日：2016-05-06

    Applicant: Artesyn Embedded Computing, Inc.

    Inventor： Shugao Ye ,  Liu Jiang ,  Kai Hu ,  Martin Peter John Cornes ,  Pasi Jukka Petteri Vaananen

    IPC: G06F12/00 ,  G06F15/173 ,  G06F9/52 ,  G06F12/06

    Abstract: A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first memory address to a first register in response to the first CPU reaching the synchronization point, and a second CPU that writes a second memory address to a second register in response to the second CPU reaching the synchronization point. The system further includes a first logical AND module that writes a first value to a third register based on the first and second memory addresses and a second logical AND module that writes a second value to a fourth register based on the first and second memory addresses. The system also includes a scheduler module that selectively generates a processor sync signal based on the first and second value.

    Integrated thermal inserts and cold plate
    9.
    发明授权
    Integrated thermal inserts and cold plate 有权

    公开(公告)号：US10039210B2

    公开(公告)日：2018-07-31

    申请号：US15616257

    申请日：2017-06-07

    Applicant: Artesyn Embedded Computing, Inc.

    Inventor： Suzanne Marye Wong ,  Martin Peter John Cornes ,  Robert Charles Tufford

    IPC: H05K7/20

    CPC classification number: H05K7/20545

    Abstract: A cooling system having integrated cold plate extending member and cold plate for an electronics enclosure includes a chassis having multiple heat producing boards positioned in side-by-side parallel configuration having successive ones of the boards separated by a cavity thereby defining multiple ones of the cavities. A cold plate assembly includes a base unit of a thermally conductive material. The cold plate assembly also includes multiple cold plate extending members connected to the base unit. Successive ones of the cold plate extending members are spaced to be slidably received in one of the cavities such that the cold plate extending member received between any two successive boards is in direct contact with both of the successive ones of the boards.

    Direct Connect Algorithm
    10.
    发明申请
    Direct Connect Algorithm 有权
    直接连接算法

    公开(公告)号：US20150293806A1

    公开(公告)日：2015-10-15

    申请号：US14251677

    申请日：2014-04-14

    Applicant: Artesyn Embedded Computing, Inc.

    Inventor： Martin Peter John CORNES ,  Gary PERKINS

    IPC: G06F11/07 ,  B61H11/00 ,  G06F11/30 ,  B61L99/00

    CPC classification number: G06F11/0751 ,  B60T13/665 ,  B60T17/228 ,  B61H11/00 ,  B61L15/0063 ,  B61L27/0061 ,  G06F11/0793 ,  G06F11/0796 ,  G06F11/1641 ,  G06F11/2038 ,  G06F11/3031 ,  G06F11/3055 ,  H04L1/00 ,  H04L1/08

    Abstract: A system includes a safety relevant component that generates a data packet in response to receiving a request to perform a task and that communicates the data packet. The system further includes a first fail-safe chassis (FSC) that continuously generates a first and second chassis health signals, that determines whether the data packet is valid, and that selectively determines whether to de-assert the first and second chassis health signals based on the determination. The system also includes a second FSC that continuously generates a third a fourth chassis health signals, that determines whether a data packet is valid, and that selectively determines whether to de-assert the third and fourth chassis health signals based on the determination. The system includes a direct connect algorithm state machine that determines whether to instruct the one of the first and second FSCs to operate in a predetermined mode based on the chassis health signals.

    Abstract translation: 系统包括响应于接收到执行任务的请求并且传送数据分组而产生数据分组的安全相关组件。 所述系统还包括：第一故障保护机箱（FSC），其连续地生成第一和第二机箱健康信号，所述第一和第二机箱健康信号确定所述数据分组是否有效，以及有选择地确定是否基于所述第一和第二机箱健康信号去断 决心。 该系统还包括第二FSC，其连续地生成第三个第四机箱健康信号，其确定数据分组是否有效，并且基于该确定来选择性地确定是否去除第三和第四机箱健康信号。 该系统包括直接连接算法状态机，其基于机箱健康信号确定是否指示第一和第二FSC中的一个以预定模式操作。

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