Invention Grant
- Patent Title: Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
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Application No.: US15654481Application Date: 2017-07-19
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Publication No.: US10346302B2Publication Date: 2019-07-09
- Inventor: Karthikeyan Avudaiyappan , Mohammad Abdallah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: NDWE LLP
- Main IPC: G06F12/12
- IPC: G06F12/12 ; G06F12/0804 ; G06F12/0811 ; G06F12/0815 ; G06F12/0897

Abstract:
A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.
Public/Granted literature
- US20180011791A1 SYSTEMS AND METHODS FOR MAINTAINING THE COHERENCY OF A STORE COALESCING CACHE AND A LOAD CACHE Public/Granted day:2018-01-11
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