Invention Grant
- Patent Title: Non-intrusive on-chip analog test/trim/calibrate subsystem
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Application No.: US15839174Application Date: 2017-12-12
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Publication No.: US10359469B2Publication Date: 2019-07-23
- Inventor: Xiankun Jin , Douglas A. Garrity
- Applicant: NXP USA, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G06F11/27
- IPC: G06F11/27 ; G01R31/317 ; G01R31/3177 ; G01R31/3187

Abstract:
An on-chip built-in self-test (BIST) circuit (10) uses a controller (16), analog-to-digital converter (ADC) (15), and digital-to-analog converter (DAC) (12) to sense voltage and/or temperature measures at predetermined circuit locations (19), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus (13) to the analog block, and to process analog test signals received over a second bus (14) from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.
Public/Granted literature
- US20190178938A1 Non-Intrusive On-Chip Analog Test/Trim/Calibrate Subsystem Public/Granted day:2019-06-13
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