公开(公告)号：US11585849B2

公开(公告)日：2023-02-21

申请号：US16460251

申请日：2019-07-02

Applicant: NXP USA, INC.

Inventor： Tao Chen ,  Xiankun Jin ,  Jan-Peter Schat

IPC: G01R31/3167 ,  G01R35/00 ,  G01R31/3177 ,  G01R31/317 ,  H03M1/66 ,  H03M7/16 ,  H03M1/10

Abstract: An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.

公开(公告)号：US10345841B1

公开(公告)日：2019-07-09

申请号：US16006247

申请日：2018-06-12

Applicant: NXP USA, INC.

Inventor： Robert S. Jones, III ,  Xiankun Jin

IPC: G05F1/63 ,  H03M1/38 ,  G01R31/28

Abstract: A current source circuit includes a first variable resistor circuit. The first variable resistor circuit includes a resistive material and a first plurality of tap inputs configured to set a resistance of the first variable resistor circuit. The current source circuit includes an output configured to provide a current. The current is adjustable by varying the resistance of the first variable resistor circuit. The current source circuit includes a second variable resistor circuit. The second variable resistor circuit includes a resistive material of a same resistive material type as the resistive material of the first variable resistor circuit. The second variable resistor circuit includes a second plurality of tap inputs configured to set a resistance of the second variable resistor circuit. Each tap resistance of the second variable resistor circuit is proportional to a corresponding tap resistance of the first variable resistor circuit. A first terminal of the second variable resistor circuit is coupled to a first test port and a second terminal of the second variable resistor circuit is coupled to a second test port to allow for a resistance measurement of the second variable resistor circuit during a test mode. The current source circuit includes a non-volatile storage circuit configured to store a tap value generated during the test mode corresponding to a set of select signal values for the second plurality of tap inputs which provides a desired resistance of the second variable resistor circuit as determined during the test mode and to provide a set of select signal values for the first plurality of tap inputs based on the tap value stored in the non-volatile storage circuit.

公开(公告)号：US11961577B2

公开(公告)日：2024-04-16

申请号：US17810671

申请日：2022-07-05

Applicant: NXP USA, Inc.

Inventor： Kumar Abhishek ,  Xiankun Jin ,  Mark Lehmann

IPC: G11C29/46 ,  G11C7/16 ,  G11C29/18 ,  H03M1/46

CPC classification number: G11C29/46 ,  G11C7/16 ,  G11C29/18 ,  H03M1/462

Abstract: Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.

公开(公告)号：US20220334176A1

公开(公告)日：2022-10-20

申请号：US17231642

申请日：2021-04-15

Applicant: NXP USA, Inc.

Inventor： Kumar Abhishek ,  Xiankun Jin ,  Srikanth Jagannathan

IPC: G01R31/28 ,  H03K3/037

Abstract: An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.

公开(公告)号：US10359469B2

公开(公告)日：2019-07-23

申请号：US15839174

申请日：2017-12-12

Applicant: NXP USA, Inc.

Inventor： Xiankun Jin ,  Douglas A. Garrity

IPC: G06F11/27 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3187

Abstract: An on-chip built-in self-test (BIST) circuit (10) uses a controller (16), analog-to-digital converter (ADC) (15), and digital-to-analog converter (DAC) (12) to sense voltage and/or temperature measures at predetermined circuit locations (19), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus (13) to the analog block, and to process analog test signals received over a second bus (14) from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.

公开(公告)号：US20190178938A1

公开(公告)日：2019-06-13

申请号：US15839174

申请日：2017-12-12

Applicant: NXP USA, Inc.

Inventor： Xiankun Jin ,  Douglas A. Garrity

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31724 ,  G01R31/31703 ,  G01R31/3177

Abstract: An on-chip built-in self-test (BIST) circuit (10) uses a controller (16), analog-to-digital converter (ADC) (15), and digital-to-analog converter (DAC) (12) to sense voltage and/or temperature measures at predetermined circuit locations (19), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus (13) to the analog block, and to process analog test signals received over a second bus (14) from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.

公开(公告)号：US20190026205A1

公开(公告)日：2019-01-24

申请号：US15652309

申请日：2017-07-18

Applicant: NXP USA, Inc.

Inventor： Xiankun Jin ,  Mark Stachew

IPC: G06F11/27

CPC classification number: G06F11/27 ,  H03M1/108 ,  H03M1/12

Abstract: Analog-to-digital conversion is tested in-field using an on-chip built-in self-test (BIST) sub-circuit formed within an underlying integrated circuit. Processing cycles may be conscripted during an idle state when the analog-to-digital conversion is not needed. The BIST requires a test time which may be compared to an idle time. If the idle time exceeds the test time, then the BIST may be entirely performed. However, if the idle time is unknown or less than the test time, the BIST may be paused and resumed between subsequent idle states.

公开(公告)号：US11728336B2

公开(公告)日：2023-08-15

申请号：US16941729

申请日：2020-07-29

Applicant: NXP USA, Inc.

Inventor： Robert S. Jones, III ,  Xiankun Jin

IPC: H01L27/08 ,  H01L23/532 ,  H01L23/522 ,  H03M1/00 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L23/5223 ,  H01L23/53204 ,  H01L28/60 ,  H01L28/87 ,  H03M1/00

Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

公开(公告)号：US20210003633A1

公开(公告)日：2021-01-07

申请号：US16460251

申请日：2019-07-02

Applicant: NXP USA, INC.

Inventor： Tao Chen ,  Xiankun Jin ,  Jan-Peter Schat

IPC: G01R31/3177 ,  H03M7/16 ,  H03M1/66 ,  G01R31/317

Abstract: An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.

公开(公告)号：US10816595B2

公开(公告)日：2020-10-27

申请号：US16165411

申请日：2018-10-19

Applicant: NXP USA, INC.

Inventor： Xiankun Jin ,  Jan-Peter Schat ,  Tao Chen ,  Lei Ma

IPC: G01R31/28

Abstract: A self-test apparatus for use in an electronic system includes an inter-chip communication bus, a plurality of circuit devices, circuitry including memory, and test controller circuitry. The plurality of circuit devices each has a distributed self-test controller circuit and analog, mixed signal or digital circuit elements. The distributed self-test controller circuits are integrated communicatively via the inter-chip communication bus and negotiate a self-test protocol with each other. The circuitry including memory stores self-test properties of the circuit elements, the self-test properties corresponding to an identifier of each of the circuit elements and a manner or protocol in which the circuit elements are tested. The test controller circuitry collects the self-test properties of the circuit elements and controls execution of the self-test according to the negotiated self-test protocol and the self-test properties.