Invention Grant
- Patent Title: Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines
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Application No.: US15354742Application Date: 2016-11-17
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Publication No.: US10372454B2Publication Date: 2019-08-06
- Inventor: Mohammad Abdallah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: NDWE LLP
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F9/30 ; G06F9/38 ; G06F9/50 ; G06F13/16 ; G06F13/40

Abstract:
A method for allocation of a segmented interconnect in an integrate circuit is disclosed. The method comprises receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences. The method also comprises contending for the plurality of resources in accordance with requests from the plurality of resource consumers. Finally, the method comprises accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of global segment buses.
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