Invention Grant
- Patent Title: FPGA mismatched packet stop for a safety system
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Application No.: US15455619Application Date: 2017-03-10
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Publication No.: US10372579B2Publication Date: 2019-08-06
- Inventor: Gary Perkins , Malcolm J. Rush , Andrew Porter
- Applicant: Artesyn Embedded Computing, Inc.
- Applicant Address: US AZ Tempe
- Assignee: Artesyn Embedded Computing, Inc.
- Current Assignee: Artesyn Embedded Computing, Inc.
- Current Assignee Address: US AZ Tempe
- Agency: Harness, Dickey & Pierce, P.L.C.
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/34 ; H04L29/06 ; G06F11/30 ; G06F11/07 ; G06F11/277 ; H04L29/08 ; H04L29/14

Abstract:
A fault-tolerant failsafe computer voting system including a first voting module that generates a first key based on a comparison between a first data packet and a copy of a second data packet. The first voting module determines whether the first key and a second key are valid keys. The second data packet is a copy of the first data packet. A second voting module generates the second key based on a comparison between the second data packet and a copy of the first data packet. A processing module generates an outgoing data packet based on the first data packet in response to determining whether the first key and the second key are valid keys. The first voting module is inhibited from generating the second key and the second voting module is inhibited from generating the first key.
Public/Granted literature
- US20180260297A1 FPGA Mismatched Packet Stop For A Safety System Public/Granted day:2018-09-13
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