Invention Grant
- Patent Title: Microelectronic devices and related methods
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Application No.: US16051886Application Date: 2018-08-01
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Publication No.: US10373974B2Publication Date: 2019-08-06
- Inventor: Eric H. Freeman , Justin B. Dorhout
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L27/11573
- IPC: H01L27/11573 ; H01L27/11575 ; H01L27/11582

Abstract:
Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. The slots are separated by a first distance in a first portion of the block, and by a second, greater distance in a second portion of the block. Methods of forming vertical memory blocks include forming slots separated by a first distance in a memory array region and by a second, greater distance in a via region. At least one conductive via is formed through a stack of alternating first and second dielectric materials in the via region.
Public/Granted literature
- US20180350836A1 SEMICONDUCTOR DEVICES AND RELATED METHODS Public/Granted day:2018-12-06
Information query
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