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    Memory devices, semiconductor devices and related methods
    1.
    发明授权
    Memory devices, semiconductor devices and related methods 有权

    公开(公告)号：US10930585B2

    公开(公告)日：2021-02-23

    申请号：US16409464

    申请日：2019-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Eric H. Freeman

    IPC: H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768

    Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

    Methods of forming semiconductor devices
    2.
    发明授权
    Methods of forming semiconductor devices 有权

    公开(公告)号：US10910310B2

    公开(公告)日：2021-02-02

    申请号：US16413470

    申请日：2019-05-15

    Applicant: Micron Technology, Inc.

    Inventor： Eric H. Freeman ,  Michael A. Smith

    IPC: H01L21/44 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

    Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

    CAPACITOR STRUCTURES HAVING IMPROVED AREA EFFICIENCY
    5.
    发明申请
    CAPACITOR STRUCTURES HAVING IMPROVED AREA EFFICIENCY 有权
    具有改善区域效能的电容器结构

    公开(公告)号：US20140198582A1

    公开(公告)日：2014-07-17

    申请号：US14216168

    申请日：2014-03-17

    Applicant: Micron Technology, Inc.

    Inventor： Eric H. Freeman

    IPC: G11C16/24

    CPC classification number: H01L28/88 ,  G11C16/102 ,  G11C16/24 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573 ,  H01L28/82

    Abstract: Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

    Abstract translation: 公开了包括其间具有介电材料的多个导电结构的半导体结构。 可以调节导电结构间隔开的电介质材料的厚度，以提供电容和电压阈值的优化。 半导体结构可以用作例如存储器件中的电容器。 可以使用各种方法来形成包括这种半导体结构的这种半导体结构和电容器。 还公开了包括这种电容器的存储器件。

    MEMORY DEVICES, SEMICONDUCTOR DEVICES AND RELATED METHODS
    7.
    发明申请
    MEMORY DEVICES, SEMICONDUCTOR DEVICES AND RELATED METHODS 审中-公开

    公开(公告)号：US20190267323A1

    公开(公告)日：2019-08-29

    申请号：US16409464

    申请日：2019-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Eric H. Freeman

    IPC: H01L23/522 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11548

    Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

    Microelectronic devices and related methods
    8.
    发明授权
    Microelectronic devices and related methods 有权

    公开(公告)号：US10373974B2

    公开(公告)日：2019-08-06

    申请号：US16051886

    申请日：2018-08-01

    Applicant: Micron Technology, Inc.

    Inventor： Eric H. Freeman ,  Justin B. Dorhout

    IPC: H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    Abstract: Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. The slots are separated by a first distance in a first portion of the block, and by a second, greater distance in a second portion of the block. Methods of forming vertical memory blocks include forming slots separated by a first distance in a memory array region and by a second, greater distance in a via region. At least one conductive via is formed through a stack of alternating first and second dielectric materials in the via region.

    VERTICAL MEMORY BLOCKS AND RELATED DEVICES AND METHODS
    9.
    发明申请
    VERTICAL MEMORY BLOCKS AND RELATED DEVICES AND METHODS 有权

    公开(公告)号：US20170141121A1

    公开(公告)日：2017-05-18

    申请号：US14942573

    申请日：2015-11-16

    Applicant: Micron Technology, Inc.

    Inventor： Eric H. Freeman ,  Justin B. Dorhout

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

    Abstract: Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. The slots are separated by a first distance in a first portion of the block, and by a second, greater distance in a second portion of the block. Methods of forming vertical memory blocks include forming slots separated by a first distance in a memory array region and by a second, greater distance in a via region. At least one conductive via is formed through a stack of alternating first and second dielectric materials in the via region.

    Conductive structures, systems and devices including conductive structures and related methods
    10.
    发明授权
    Conductive structures, systems and devices including conductive structures and related methods 有权
    导电结构，系统和装置，包括导电结构和相关方法

    公开(公告)号：US09536823B2

    公开(公告)日：2017-01-03

    申请号：US14308339

    申请日：2014-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Eric H. Freeman

    IPC: H01L23/00 ,  H01L23/522 ,  H01L27/115 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

    Abstract translation: 导电结构包括多个导电台阶和至少部分地穿过其延伸的接触件，与多个导电台阶中的至少一个连通，并与至少另一导电台阶绝缘。 设备可以包括这种导电结构。 系统可以包括半导体器件和楼梯级导电结构，其具有延伸穿过楼梯级导电结构的台阶的多个触点。 形成导电结构的方法包括在通过导电结构的至少一个导电步骤形成的接触孔中形成接触。 在楼梯级导电结构中形成电连接的方法包括在通过楼梯级导电结构的每个步骤形成的接触孔中形成触点。

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