Invention Grant
- Patent Title: Zero current and valley detection for power factor correction
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Application No.: US15854467Application Date: 2017-12-26
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Publication No.: US10411592B2Publication Date: 2019-09-10
- Inventor: Ananthakrishnan Viswanathan , Salvatore Giombanco , Joseph Michael Leisten , Philomena Cleopha Brady
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Tuenlap Chan; Charles A. Brill; Frank D. Cimino
- Main IPC: H02M1/42
- IPC: H02M1/42 ; H02M7/06 ; H02M7/217 ; H02M1/00

Abstract:
A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.
Public/Granted literature
- US20190199203A1 ZERO CURRENT AND VALLEY DETECTION FOR POWER FACTOR CORRECTION Public/Granted day:2019-06-27
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