Invention Grant
- Patent Title: Arrangement and thermal management of 3D stacked dies
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Application No.: US15686558Application Date: 2017-08-25
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Publication No.: US10431517B2Publication Date: 2019-10-01
- Inventor: John Wuu , Samuel Naffziger , Patrick J. Shyvers , Milind S. Bhagavat , Kaushik Mysore , Brett P. Wilkerson
- Applicant: John Wuu , Samuel Naffziger , Patrick J. Shyvers , Milind S. Bhagavat , Kaushik Mysore , Brett P. Wilkerson
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agent Timothy M. Honeycutt
- Main IPC: H01L23/367
- IPC: H01L23/367 ; H01L25/00 ; H01L25/065 ; H01L23/36 ; H01L23/373
Abstract:
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
Public/Granted literature
- US20190067152A1 ARRANGEMENT AND THERMAL MANAGEMENT OF 3D STACKED DIES Public/Granted day:2019-02-28
Information query
IPC分类:
