Invention Grant
- Patent Title: Reduced capacitance land pad
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Application No.: US13727439Application Date: 2012-12-26
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Publication No.: US10433421B2Publication Date: 2019-10-01
- Inventor: Zhichao Zhang , Tao Wu , Gaurav Chawla , Jeffrey Lee
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/02 ; H05K3/34

Abstract:
A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.
Public/Granted literature
- US20140174808A1 REDUCED CAPACITANCE LAND PAD Public/Granted day:2014-06-26
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