Invention Grant
- Patent Title: Vertical field effect transistor with strained channel region extension
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Application No.: US16018289Application Date: 2018-06-26
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Publication No.: US10453940B1Publication Date: 2019-10-22
- Inventor: Shogo Mochizuki , Choonghyun Lee , Juntao Li , Kangguo Cheng
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/08 ; H01L29/06 ; H01L29/10

Abstract:
According to one or more embodiments of the present invention, a method for forming a fin structure for a semiconductor device includes forming a fin. The method further includes recessing a first portion of the fin to form a recess in the fin. The method further includes forming a channel region in the first portion of the fin. The method further includes forming an extension region on a second portion of the fin, and wherein defects are collected within the extension regions from the channel region in the first portion of the fin.
Information query
IPC分类: