Invention Grant
- Patent Title: Solder in cavity interconnection structures
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Application No.: US15884167Application Date: 2018-01-30
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Publication No.: US10468367B2Publication Date: 2019-11-05
- Inventor: Chuan Hu , Shawna M. Liff , Gregory S. Clemons
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H05K1/18 ; H01L21/56 ; H01L23/31 ; H01L23/498

Abstract:
The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.
Public/Granted literature
- US20180151529A1 SOLDER IN CAVITY INTERCONNECTION STRUCTURES Public/Granted day:2018-05-31
Information query
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