Invention Grant
- Patent Title: Methods of forming merged source/drain regions on integrated circuit products
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Application No.: US15868004Application Date: 2018-01-11
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Publication No.: US10475904B2Publication Date: 2019-11-12
- Inventor: Hiroaki Niimi , Steven Bentley , Romain Lallement , Brent A. Anderson , Junli Wang , Muthumanickam Sankarapandian
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/778 ; H01L27/092 ; H01L21/8234 ; H01L27/11 ; H01L21/8238

Abstract:
A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region.
Public/Granted literature
- US20190214484A1 METHODS OF FORMING MERGED SOURCE/DRAIN REGIONS ON INTEGRATED CIRCUIT PRODUCTS Public/Granted day:2019-07-11
Information query
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