Invention Grant
- Patent Title: 3D stacked dies with disparate interconnect footprints
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Application No.: US15826054Application Date: 2017-11-29
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Publication No.: US10529693B2Publication Date: 2020-01-07
- Inventor: Rahul Agarwal , Milind S. Bhagavat
- Applicant: Rahul Agarwal , Milind S. Bhagavat
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agent Timothy M. Honeycutt
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L23/538 ; H01L23/522 ; H01L23/498 ; H01L21/48 ; H01L23/48

Abstract:
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a front side and a back side and plural through chip vias. The through chip vias have a first footprint. The back side is configured to have a second semiconductor chip stacked thereon. The second semiconductor chip includes plural interconnects that have a second footprint larger than the first footprint. The back side includes a backside interconnect structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias.
Public/Granted literature
- US20190164936A1 3D STACKED DIES WITH DISPARATE INTERCONNECT FOOTPRINTS Public/Granted day:2019-05-30
Information query
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