- Patent Title: Nanowire structures having non-discrete source and drain regions
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Application No.: US15405899Application Date: 2017-01-13
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Publication No.: US10580899B2Publication Date: 2020-03-03
- Inventor: Stephen M. Cea , Annalisa Cappellani , Martin D. Giles , Rafael Rios , Seiyon Kim , Kelin J. Kuhn
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L29/08 ; H01L21/268 ; H01L29/78 ; B82Y40/00

Abstract:
Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.
Public/Granted literature
- US20170141239A1 NANOWIRE STRUCTURES HAVING NON-DISCRETE SOURCE AND DRAIN REGIONS Public/Granted day:2017-05-18
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