Invention Grant
- Patent Title: Systems and methods for non-blocking implementation of cache flush instructions
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Application No.: US15806178Application Date: 2017-11-07
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Publication No.: US10585804B2Publication Date: 2020-03-10
- Inventor: Karthikeyan Avudaiyappan , Mohammad Abdallah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: NDWE, LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0891 ; G06F12/0811 ; G06F12/0804 ; G06F12/0837 ; G06F12/0897

Abstract:
Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged.
Public/Granted literature
- US20180060243A1 SYSTEMS AND METHODS FOR NON-BLOCKING IMPLEMENTATION OF CACHE FLUSH INSTRUCTIONS Public/Granted day:2018-03-01
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