Invention Grant
- Patent Title: Fabrication of vertical field effect transistor structure with strained channels
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Application No.: US15628102Application Date: 2017-06-20
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Publication No.: US10586858B2Publication Date: 2020-03-10
- Inventor: Kangguo Cheng , Juntao Li
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/786 ; H01L27/088 ; H01L21/8234 ; H01L29/06 ; H01L29/423

Abstract:
A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.
Public/Granted literature
- US20170330969A1 Fabrication Of Vertical Field Effect Transistor Structure With Strained Channels Public/Granted day:2017-11-16
Information query
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