A memory device with crossbar array structure includes two sets of parallel bottom electrodes positioned on a substrate. The lower bottom electrodes are located at a lower position relative to higher bottom electrodes. The device includes a first set of corner tips of the lower bottom electrodes, and a second set of corner tips at a top of the higher bottom electrodes. The device also includes a set of parallel top electrodes intersecting the two sets of parallel bottom electrodes. A dielectric is formed as a resistive random-access memory (RRAM) cell under each intersection of each top electrode and each of bottom electrode. The device further includes one set of contacts at one end of an array that contacts the lower bottom electrodes and another set of contacts at the other end of the array that contacts the higher bottom electrodes.