Invention Grant
- Patent Title: Local cell-level power gating switch
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Application No.: US15755021Application Date: 2015-09-25
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Publication No.: US10659046B2Publication Date: 2020-05-19
- Inventor: Rafael Rios , Van Le , Gilbert Dewey , Jack T. Kavalieros
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/052490 WO 20150925
- International Announcement: WO2017/052657 WO 20170330
- Main IPC: H03K19/00
- IPC: H03K19/00 ; G06F30/30 ; G06F30/39 ; G06F1/3203 ; H01L27/02 ; H03K19/094

Abstract:
A power gating switch is described at a local cell level of an integrated circuit die. In one example a plurality of logic cells have a data input line and a data output line and a power supply input to receive power to drive circuits of the logic cell. A power switch for each logic cell is coupled between a power supply and the power supply input of the respective logic cell to control power being connected from the power supply to the respective logic cell.
Public/Granted literature
- US20180254778A1 LOCAL CELL-LEVEL POWER GATING SWITCH Public/Granted day:2018-09-06
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