Invention Grant
- Patent Title: Package including an integrated routing layer and a molded routing layer
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Application No.: US15853173Application Date: 2017-12-22
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Publication No.: US10665522B2Publication Date: 2020-05-26
- Inventor: Lizabeth Keser , Thomas Ort , Thomas Wagner , Bernd Waidhas
- Applicant: Intel IP Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel IP Corporation
- Current Assignee: Intel IP Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/48 ; H01L21/56 ; H01L21/78 ; H01L21/66 ; H01L23/538 ; H01L23/00
Abstract:
A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
Public/Granted literature
- US20190198478A1 FAN OUT PACKAGE AND METHODS Public/Granted day:2019-06-27
Information query
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