公开(公告)号：US11145577B2

公开(公告)日：2021-10-12

申请号：US16349359

申请日：2016-12-29

Applicant: Intel IP Corporation

Inventor： Sonja Koller ,  Georg Seidemann ,  Reinhard Mahnkopf ,  Bernd Waidhas

IPC: H01L23/495 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: A system-in-package apparatus includes a square wave lead frame that provides a recess for a first semiconductive device as well as a feature for a second device. The system-in-package apparatus includes a printed wiling board that is wrapped onto the lead frame after a manner to enclose the first semiconductive device into the recess.

公开(公告)号：US20200251396A1

公开(公告)日：2020-08-06

申请号：US16855418

申请日：2020-04-22

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/66 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US20190206799A1

公开(公告)日：2019-07-04

申请号：US15857189

申请日：2017-12-28

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/16 ,  H01L25/00

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0233 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/145 ,  H01L2924/15153 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351

Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

公开(公告)号：US10115668B2

公开(公告)日：2018-10-30

申请号：US14970355

申请日：2015-12-15

Applicant: Intel IP Corporation

Inventor： Klaus Jürgen Reingruber ,  Sven Albers ,  Christian Georg Geissler ,  Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/522 ,  H01L23/528 ,  C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  C25D5/54 ,  C25D7/12 ,  H01L23/00 ,  H05K1/02 ,  H05K1/11 ,  H01L23/498

Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

公开(公告)号：US20170178999A1

公开(公告)日：2017-06-22

申请号：US14977307

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Richard Patten ,  Bernd Waidhas ,  Sonja Koller

IPC: H01L23/373 ,  H01L23/31

CPC classification number: H01L23/3736 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83

Abstract: Embodiments herein may relate to a flip-chip chip scale package (FCCSP) with a thermal dissipation layer to dissipate heat from the FCCSP during operation of the FCCSP. The thermal dissipation layer may be applied to a surface of the FCCSP through a sputter coating process and may operate as a heat spreader for the FCCSP. Other embodiments may be described and/or claimed.

公开(公告)号：US11031699B2

公开(公告)日：2021-06-08

申请号：US15892632

申请日：2018-02-09

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC: H01Q19/06 ,  H01Q15/08 ,  H01L23/66 ,  H01L23/528 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/13 ,  H01Q1/48

Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

公开(公告)号：US11018114B2

公开(公告)日：2021-05-25

申请号：US16515979

申请日：2019-07-18

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/10 ,  H01L25/065 ,  H01L21/48 ,  H01L23/48 ,  H01L25/00 ,  H01L23/427 ,  G06F15/76

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US10699980B2

公开(公告)日：2020-06-30

申请号：US15938741

申请日：2018-03-28

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Bernd Waidhas ,  Thomas Ort ,  Thomas Wagner

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

公开(公告)号：US20190304922A1

公开(公告)日：2019-10-03

申请号：US15937542

申请日：2018-03-27

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Thomas Ort ,  Andreas Wolter ,  Andreas Augustin ,  Veronica Sciriha ,  Bernd Waidhas

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/64

Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.

公开(公告)号：US10403580B2

公开(公告)日：2019-09-03

申请号：US15858103

申请日：2017-12-29

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.