Invention Grant
- Patent Title: Semiconductor devices with raised doped crystalline structures
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Application No.: US16242949Application Date: 2019-01-08
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Publication No.: US10665708B2Publication Date: 2020-05-26
- Inventor: Marko Radosavljevic , Sansaptak Dasgupta , Sanaz K. Gardner , Seung Hoon Sung , Han Wui Then , Robert S. Chau
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L29/778 ; H01L29/66 ; H01L29/06 ; H01L21/02 ; H01L21/8258 ; H01L29/08 ; H01L29/205 ; H01L29/20 ; H01L21/8234 ; H01L21/8252

Abstract:
Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.
Public/Granted literature
- US20190148533A1 SEMICONDUCTOR DEVICES WITH RAISED DOPED CRYSTALLINE STRUCTURES Public/Granted day:2019-05-16
Information query
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