公开(公告)号：US12080763B2

公开(公告)日：2024-09-03

申请号：US17826058

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/20 ,  H01L21/033 ,  H01L21/285 ,  H01L21/321 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/0337 ,  H01L21/28575 ,  H01L21/3212 ,  H01L21/76802 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/778

Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.

公开(公告)号：US11799057B2

公开(公告)日：2023-10-24

申请号：US17530725

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic

IPC: H01L33/32 ,  H01L33/00 ,  H01L33/06 ,  H01L33/62

CPC classification number: H01L33/325 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/62

Abstract: Light emitting devices employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge carrier sheet within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening material layer between two III-N material layers. Where a light emitting structure includes a quantum well (QW) structure between two Group III-Nitride polarization junctions, a 2D electron gas (2DEG) induced at a first polarization junction and/or a 2D hole gas (2DHG) induced at a second polarization junction on either side of the QW structure may supply carriers to the QW structure. An improvement in quantum efficiency may be achieved where the intervening material layer further functions as a barrier to carrier recombination outside of the QW structure.

公开(公告)号：US20230207421A1

公开(公告)日：2023-06-29

申请号：US17561463

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid M. Hafez

IPC: H01L23/38 ,  H01L27/16 ,  H01L35/34

CPC classification number: H01L23/38 ,  H01L27/16 ,  H01L35/34

Abstract: Technologies for thermoelectric enhanced cooling on an integrated circuit die are disclosed. In the illustrative embodiment, one or more components are created on a top side of an integrated circuit die, such as a power amplifier, logic circuitry, etc. The one or more components, in use, generate heat that needs to be carried away from the components. A thermoelectric cooler can be created on a back side of the die in order to facilitate removal of heat from the component. In some embodiments, additional structures such as vias filled with high-thermal-conductivity material may be used to further improve the removal of heat from the component.

公开(公告)号：US11688788B2

公开(公告)日：2023-06-27

申请号：US16209039

申请日：2018-12-04

Applicant: INTEL CORPORATION

Inventor： Johann C. Rode ,  Samuel J. Beach ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Walid Hafez

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/513 ,  H01L21/022 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/28158 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.

公开(公告)号：US11671075B2

公开(公告)日：2023-06-06

申请号：US16998389

申请日：2020-08-20

Applicant: INTEL CORPORATION

Inventor： Sansaptak Dasgupta ,  Bruce A. Block ,  Paul B. Fischer ,  Han Wui Then ,  Marko Radosavljevic

IPC: H03H9/205 ,  H03H9/13 ,  H03H9/17 ,  H03H9/15 ,  H03H9/02

CPC classification number: H03H9/205 ,  H03H9/02007 ,  H03H9/02543 ,  H03H9/02574 ,  H03H9/13 ,  H03H9/15 ,  H03H9/172 ,  H03H2009/02173

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion having a different resonator thickness. Each wing may also have different thicknesses. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.

公开(公告)号：US11664417B2

公开(公告)日：2023-05-30

申请号：US16130911

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Walid Hafez ,  Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul Fischer

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8236 ,  H01L29/51 ,  H01L29/20

CPC classification number: H01L29/0638 ,  H01L21/8236 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/51

Abstract: Integrated circuits with III-N metal-insulator-semiconductor field effect transistor (MISFET) structures that employ one or more gate dielectric materials that differ across the MISFETs. Gate dielectric materials may be selected to modulate dielectric breakdown strength and/or threshold voltage between transistors. Threshold voltage may be modulated between two MISFET structures that may be substantially the same but for the gate dielectric. Control of the gate dielectric material may render some MISFETs to be operable in depletion mode while other MISFETs are operable in enhancement mode. Gate dielectric materials may be varied by incorporating multiple dielectric materials in some MISFETs of an IC while other MISFETs of the IC may include only a single dielectric material. Combinations of gate dielectric material layers may be selected to provide a menu of low voltage, high voltage, enhancement and depletion mode MISFETs within an IC.

公开(公告)号：US11658217B2

公开(公告)日：2023-05-23

申请号：US16242670

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Glenn A. Glass ,  Sansaptak Dasgupta ,  Nidhi Nidhi ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/00 ,  H01L29/40 ,  H01L21/265 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L29/405 ,  H01L21/265 ,  H01L29/205 ,  H01L29/404 ,  H01L29/408 ,  H01L29/7786

Abstract: Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor. Ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.

公开(公告)号：US11626513B2

公开(公告)日：2023-04-11

申请号：US16218886

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Nidhi Nidhi ,  Walid M. Hafez ,  Johann C. Rode ,  Paul Fischer ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Heli Chetanbhai Vora

IPC: H01L29/417 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/43 ,  H01L21/285 ,  H01L29/40 ,  H01L21/02 ,  H01L29/20

Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

公开(公告)号：US20220399305A1

公开(公告)日：2022-12-15

申请号：US17342826

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  Adel A. Elsherbini ,  Han Wui Then ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552 ,  H01L23/66 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, embedded in a first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a first magnetic conductive material; and a second microelectronic component, embedded in a second dielectric layer on the first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a second magnetic conductive material, wherein the second microelectronic component is coupled to the surface of the first microelectronic component by a hybrid bonding region, and wherein the second magnetic conductive material is coupled to the first magnetic conductive material.

公开(公告)号：US11489061B2

公开(公告)日：2022-11-01

申请号：US16139248

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dusgupta ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: A transistor comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A gate stack is above the channel region, the gate stack comprises a gate electrode and a composite gate dielectric stack, wherein the composite gate dielectric stack comprises a first large bandgap oxide layer, a low bandgap oxide layer, and a second large bandgap oxide layer to provide a programmable voltage threshold. Source and drain regions are adjacent to the channel region.