Method for measuring the density of a semiconductor device layout
Abstract:
A method for determining a density of an integrated circuit layout includes analyzing the IC layout represented by polygons. A portion of the IC layout is analyzed within a sample window located at a sample point. A local density of polygons within the sample window is determined, where an area of one or more of the polygons within the sample window is weighted according to a weighting function giving unequal weight to polygon area based on a position within the sample window. The local density values at each sample point in an array of sample points can be used to determine a layout density and to identify locations of density violations.
Information query
Patent Agency Ranking
0/0