- Patent Title: Method for measuring the density of a semiconductor device layout
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Application No.: US16170187Application Date: 2018-10-25
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Publication No.: US10671794B1Publication Date: 2020-06-02
- Inventor: Stefan Halama , Saravanan Padmanaban , Phanindra Bhagavatula
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- Main IPC: G06F30/398
- IPC: G06F30/398

Abstract:
A method for determining a density of an integrated circuit layout includes analyzing the IC layout represented by polygons. A portion of the IC layout is analyzed within a sample window located at a sample point. A local density of polygons within the sample window is determined, where an area of one or more of the polygons within the sample window is weighted according to a weighting function giving unequal weight to polygon area based on a position within the sample window. The local density values at each sample point in an array of sample points can be used to determine a layout density and to identify locations of density violations.
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