Invention Grant
- Patent Title: Schottky diodes on semipolar planes of group III-N material structures
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Application No.: US16322816Application Date: 2016-09-28
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Publication No.: US10672884B2Publication Date: 2020-06-02
- Inventor: Sansaptak Dasgupta , Marko Radosavljevic , Han Wui Then , Paul B. Fischer
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- International Application: PCT/US2016/054189 WO 20160928
- International Announcement: WO2018/063191 WO 20180405
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/872 ; H01L29/20 ; H01L27/02 ; H01L27/06 ; H01L21/8252 ; H01L29/06 ; H01L29/778 ; H01L29/205 ; H01L21/762 ; H01L29/08 ; H01L29/423

Abstract:
Techniques are disclosed for forming Schottky diodes on semipolar planes of group III-nitride (III-N) material structures. A lateral epitaxial overgrowth (LEO) scheme may be used to form the group III-N material structures upon which Schottky diodes can then be formed. The LEO scheme for forming III-N structures may include forming shallow trench isolation (STI) material on a semiconductor substrate, patterning openings in the STI, and growing the III-N material on the semiconductor substrate to form structures that extend through and above the STI openings, for example. A III-N structure may be formed using only a single STI opening, where such a III-N structure may have a triangular prism-like shape above the top plane of the STI layer. Further processing can include forming the gate (e.g., Schottky gate) and tied together source/drain regions on semipolar planes (or sidewalls) of the III-N structure to form a two terminal Schottky diode.
Public/Granted literature
- US20190189771A1 TECHNIQUES FOR FORMING SCHOTTKY DIODES ON SEMIPOLAR PLANES OF GROUP III-N MATERIAL STRUCTURES Public/Granted day:2019-06-20
Information query
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