Invention Grant
- Patent Title: Techniques for detecting and correcting errors in data
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Application No.: US15908205Application Date: 2018-02-28
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Publication No.: US10678636B2Publication Date: 2020-06-09
- Inventor: David M. Durham
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/10 ; H04L9/06 ; G09C1/00 ; G11C29/52 ; G11C29/04

Abstract:
Various embodiments are generally directed to techniques for managing errors in data, such as with error-correcting code (ECC), for instance. Some embodiments are particularly directed to providing one or more of error detection, location, and correction for a set of storage memory devices with a management memory device. In one or more embodiments, each of the storage and management memory devices may include a memory chip, such as one of a set of memory chips included in a dual in-line memory module (DIMM). For instance, each memory device be a dynamic random-access memory (DRAM) integrated circuit included in a DIMM. In various embodiments, the set of storage management memory devices may be used to store a memory line, such as an evicted cache line. In many embodiments, cryptographically secure memory encryption and/or integrity may also be provided for the set of storage memory devices with the management memory device.
Public/Granted literature
- US20190042359A1 TECHNIQUES FOR DETECTING AND CORRECTING ERRORS IN DATA Public/Granted day:2019-02-07
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