A memory apparatus and a majority detector thereof are provided. The majority detector includes a pull-up circuit, a first switch, a second switch, a plurality of first transistors, a plurality of second transistors and a sense amplifying circuit. The pull-up circuit provides a first voltage to a first node and a second node according to a control signal before a sensing period. The first switch and the second switch provide a second voltage to the first node and the second node respectively according to the control signal during the sensing period. Control ends of the first transistors each receives one of a plurality of values of a data signal. Control ends of the second transistors each receives an inverse value of the one of the values of the data signal. The sense amplifying circuit generates a sensing result according to a voltage difference between the first node and the second node during the sensing period, and the sensing result indicates a majority value among the values.