公开(公告)号：US12300612B2

公开(公告)日：2025-05-13

申请号：US17731180

申请日：2022-04-27

Applicant: Winbond Electronics Corp.

Inventor： Yoshinori Tanaka ,  Wei-Che Chang

IPC: H10B12/00 ,  G11C5/06 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor structure includes a substrate, a trench, a first conductive layer, a second conductive layer, a third conductive layer, a source region and a drain region, a bit line contact, and a storage node contact. The trench is disposed in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed on a top surface of the first conductive layer. The third conductive layer is disposed on the top surface of the first conductive layer and is electrically connected to the second conductive layer. The source region and the drain region are disposed in the substrate and disposed on opposite sides of the first conductive layer. The bit line contact is disposed on one of the source region and the drain region, and the storage node contact is disposed on the other of the source region and the drain region.

公开(公告)号：US20250151255A1

公开(公告)日：2025-05-08

申请号：US19016032

申请日：2025-01-10

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ping HSIAO ,  Cheol-Soo PARK ,  Chun-Hung CHENG ,  Wei-Chieh CHUANG ,  Wei-Chao CHOU ,  Yen-Min JUAN

IPC: H10B12/00 ,  H01G4/008 ,  H01G4/01

Abstract: A capacitor includes cup-shaped lower electrodes disposed on a substrate, a capacitor dielectric layer conformally covering inner surfaces and outer surfaces of the cup-shaped lower electrodes, and a support layer disposed between outer surfaces of the cup-shaped lower electrodes to connect the cup-shaped lower electrodes. The capacitor further includes an annealed oxide layer, which is interposed between the inner surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer, and is also interposed between a portion of the outer surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer. A method for forming the capacitor is also provided.

公开(公告)号：US12288689B2

公开(公告)日：2025-04-29

申请号：US17857030

申请日：2022-07-03

Applicant: Winbond Electronics Corp.

Inventor： Pei-Hsiu Peng ,  Hung-Yu Wei

IPC: H01L21/033 ,  H01L21/66

Abstract: Provided is a semiconductor structure including multiple pairs of target patterns, a first conductive line, and a second conductive line. Each of the pairs of target patterns includes a top pattern and a bottom pattern. The first conductive line is disposed on a first side of the pairs of target patterns. The first conductive line is electrically connected to a top pattern of a (aN+1)th pair of target patterns in the pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is an integer greater than or equal to 0. The second conductive line is disposed on a second side of the pairs of target patterns opposite to the first side. The second conductive line is electrically connected to a bottom pattern of the (aN+1)th pair of target patterns in the pairs of target patterns.

公开(公告)号：US12283334B2

公开(公告)日：2025-04-22

申请号：US18366690

申请日：2023-08-08

Applicant: Winbond Electronics Corp.

Inventor： Shih-Hung Chen

IPC: G11C29/56

Abstract: Disclosed are a method and an apparatus for memory testing. The method comprises following steps: using a test program group including N test programs to test M dies respectively to generate independent N test data, wherein N and M are positive integers greater than 1; and executing a neural network operation on the N test data to estimate a yield of M dies passing the test program group.

公开(公告)号：US12262528B2

公开(公告)日：2025-03-25

申请号：US17973558

申请日：2022-10-26

Applicant: Winbond Electronics Corp.

Inventor： Keng-Ping Lin ,  Shu-Ming Li ,  Tzu-Ming Ou Yang

IPC: H10B12/00

Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.

公开(公告)号：US20250098250A1

公开(公告)日：2025-03-20

申请号：US18780512

申请日：2024-07-23

Applicant: Winbond Electronics Corp.

Inventor： Noriaki Ikeda ,  Chun-Sheng Yang ,  Hao-Chuan Chang

IPC: H01L29/161 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor structure including a substrate, a first electrode, a first dielectric layer, and a second electrode is provided. The first electrode is located on the substrate. The first electrode is pillar-shaped. The first dielectric layer is located on the first electrode. The second electrode is located on the first dielectric layer. The second electrode includes a first silicon germanium (SiGe) layer and a second SiGe layer. The first SiGe layer is located on the first dielectric layer. The second SiGe layer is located on the first SiGe layer. A content of germanium in the second SiGe layer is greater than a content of germanium in the first SiGe layer.

公开(公告)号：US20250098156A1

公开(公告)日：2025-03-20

申请号：US18966744

申请日：2024-12-03

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che CHANG ,  Kai JEN ,  Yu-Po WANG

IPC: H10B12/00

Abstract: A method for forming a semiconductor structure includes the following steps. A first trench is formed in a semiconductor substrate, and a first nitride layer is formed along a sidewall and a bottom surface of the first trench. A first oxide layer is formed over the first nitride layer to fill the first trench, and the first oxide layer is recessed from the first trench to form a first recess. A portion of the first nitride layer exposed from the first recess is etched, and a second nitride layer is formed along a sidewall and a bottom surface of the first recess. The second nitride layer includes a first portion along the bottom surface and a second portion along the sidewall. The second portion is removed, and a second oxide layer is formed over the first portion to fill the first recess.

公开(公告)号：US12249365B2

公开(公告)日：2025-03-11

申请号：US18178958

申请日：2023-03-06

Applicant: Winbond Electronics Corp.

Inventor： Shu-Sen Lin

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  H03K19/20

Abstract: A memory device capable of performing in-memory computing is provided and includes a memory cell array, a sense amplifier, a voltage control circuit, and a word line decoding circuit. The memory cell array includes memory cells arranged in a two-dimensional array. The memory cells on each row of the memory cell array are connected to a corresponding word line, and the memory cells on each column of the memory cell array are connected to a corresponding bit line. The sense amplifier detects a voltage level of the activated bit line and a voltage level of an inverse bit line corresponding to the bit line. The voltage control circuit selects a detection voltage provided to the sense amplifier according to a control signal from a memory controller. The word line decoding circuit activates a first word line and a second word line according to the control signal.

公开(公告)号：US20250079315A1

公开(公告)日：2025-03-06

申请号：US18677434

申请日：2024-05-29

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting CHEN ,  Yao-Ting TSAI ,  Bo-Lun WU ,  Sih-Han CHEN

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: The method for forming the semiconductor structure includes the following steps. A substrate that is divided into a cell region and a peripheral region is provided. A bottom dielectric layer is formed on the substrate. A first stacked structure and a second stacked structure are formed on the bottom dielectric layer. The first stacked structure is disposed in the cell region and the second stacked structure is disposed in the peripheral region. The first stacked structure is patterned to form first conductive stacks. A first cleaning process is performed. A first repair dielectric layer is formed on the first conductive stacks, the second stacked structure, and the bottom dielectric layer. The second stacked structure is patterned to form second conductive stacks. A second cleaning process is performed. A second repair dielectric layer is formed on the first conductive stacks, the second conductive stacks, and the bottom dielectric layer.

公开(公告)号：US12224030B2

公开(公告)日：2025-02-11

申请号：US17987435

申请日：2022-11-15

Applicant: Winbond Electronics Corp.

Inventor： Takahiko Sato

IPC: G11C29/52 ,  G11C11/4093 ,  G11C11/4096

Abstract: The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.