Invention Grant
- Patent Title: Error reducing matrix generation
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Application No.: US15725255Application Date: 2017-10-04
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Publication No.: US10679718B2Publication Date: 2020-06-09
- Inventor: Mai Ghaly , Chandan Mishra , Amir Hossein Gholamipour , Yuheng Zhang , Jeffrey Koon Yee Lee , James Hart , Daniel Helmick
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: Kunzler Bean & Adamson, PC
- Main IPC: G11C29/38
- IPC: G11C29/38 ; G11C29/36 ; G11C29/52 ; G11C29/44 ; G11C29/42 ; G11C29/00 ; G11C29/50

Abstract:
Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.
Public/Granted literature
- US20190103168A1 ERROR REDUCING MATRIX GENERATION Public/Granted day:2019-04-04
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