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公开(公告)号:US11056206B2
公开(公告)日:2021-07-06
申请号:US15851092
申请日:2017-12-21
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Amir Gholamipour , Chandan Mishra
IPC: G11C16/34 , G06F12/02 , G06F12/06 , G06F3/06 , G11C11/406 , G11C29/00 , G11C16/08 , G11C8/12 , G11C13/00
Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to group physical addresses of the set of non-volatile memory cells into groups of configurable sizes and to individually apply wear leveling schemes to non-volatile memory cells of a group.
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公开(公告)号:US10540100B2
公开(公告)日:2020-01-21
申请号:US15949976
申请日:2018-04-10
Applicant: Western Digital Technologies, Inc.
Inventor: Amir Hossein Gholamipour , Chandan Mishra , Daniel Helmick
IPC: G06F3/00 , G06F3/06 , G06F12/1009
Abstract: Apparatuses, systems, and methods are disclosed for mapping-based wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may maintain a logical-to-physical mapping for converting logical addresses to physical addresses. A logical-to-physical mapping may include a translation table that associates groups of logical addresses with groups of physical addresses, and one or more mathematical mappings. A mathematical mapping for a group of logical addresses may associate individual logical addresses within the group of logical addresses with individual physical addresses within a corresponding group of physical addresses. A controller may change at least one mathematical mapping. A controller may move data based on at least one changed mapping.
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公开(公告)号:US10409716B2
公开(公告)日:2019-09-10
申请号:US15838201
申请日:2017-12-11
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Amir Gholamipour , Chandan Mishra
Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to remap logical addresses to physical addresses of the set of non-volatile memory cells according to a plurality of placement mappings and to select a new placement mapping from the plurality of placement mappings according to a cost function associated with the new placement mapping.
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公开(公告)号:US10379950B2
公开(公告)日:2019-08-13
申请号:US15828425
申请日:2017-11-30
Applicant: Western Digital Technologies, Inc.
Inventor: Amir H. Gholamipour , Chandan Mishra , Mai Ghaly , Majid Nemati Anaraki
Abstract: Systems, apparatuses, methods, and computer program products are disclosed for updating data of write-in-place storage devices. One system includes a write-in-place memory device including a redundant storage structure and a controller for the memory device. A memory device is configured to store data across a set of stripes of a redundant storage structure. A controller is configured to receive updated data for a dataset stored across a first stripe, generate a new parity for the dataset based on the updated data, overwrite the dataset across the first stripe with the updated data, and/or write the new parity to the set of stripes.
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公开(公告)号:US20190107957A1
公开(公告)日:2019-04-11
申请号:US15730511
申请日:2017-10-11
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Daniel Helmick , Amir Gholamipour , Chandan Mishra
Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to map the set of non-volatile memory cells into a plurality of regions, apply a first wear leveling scheme in a first region of the plurality of regions, and apply a second wear leveling scheme between the plurality of regions.
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公开(公告)号:US10656844B2
公开(公告)日:2020-05-19
申请号:US15730511
申请日:2017-10-11
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Daniel Helmick , Amir Gholamipour , Chandan Mishra
Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to map the set of non-volatile memory cells into a plurality of regions, apply a first wear leveling scheme in a first region of the plurality of regions, and apply a second wear leveling scheme between the plurality of regions.
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公开(公告)号:US20190310780A1
公开(公告)日:2019-10-10
申请号:US15949976
申请日:2018-04-10
Applicant: Western Digital Technologies, Inc.
Inventor: Amir Hossein Gholamipour , Chandan Mishra , Daniel Helmick
IPC: G06F3/06 , G06F12/1009
Abstract: Apparatuses, systems, and methods are disclosed for mapping-based wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may maintain a logical-to-physical mapping for converting logical addresses to physical addresses. A logical-to-physical mapping may include a translation table that associates groups of logical addresses with groups of physical addresses, and one or more mathematical mappings. A mathematical mapping for a group of logical addresses may associate individual logical addresses within the group of logical addresses with individual physical addresses within a corresponding group of physical addresses. A controller may change at least one mathematical mapping. A controller may move data based on at least one changed mapping.
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公开(公告)号:US11301369B2
公开(公告)日:2022-04-12
申请号:US16256994
申请日:2019-01-24
Applicant: Western Digital Technologies, Inc.
Inventor: Amir Hossein Gholamipour , Mark David Myran , Chandan Mishra , Namhoon Yoo , Jun Tao
IPC: G06F12/00 , G06F11/00 , G06F12/02 , G06F11/14 , G06F12/0804
Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.
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公开(公告)号:US10679718B2
公开(公告)日:2020-06-09
申请号:US15725255
申请日:2017-10-04
Applicant: Western Digital Technologies, Inc.
Inventor: Mai Ghaly , Chandan Mishra , Amir Hossein Gholamipour , Yuheng Zhang , Jeffrey Koon Yee Lee , James Hart , Daniel Helmick
Abstract: Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.
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公开(公告)号:US11789860B2
公开(公告)日:2023-10-17
申请号:US17694470
申请日:2022-03-14
Applicant: Western Digital Technologies, Inc.
Inventor: Amir Hossein Gholamipour , Mark David Myran , Chandan Mishra , Namhoon Yoo , Jun Tao
IPC: G06F11/00 , G06F12/00 , G06F12/02 , G06F11/14 , G06F12/0804
CPC classification number: G06F12/0246 , G06F11/1441 , G06F11/1471 , G06F12/0804 , G06F2201/81 , G06F2201/84 , G06F2212/1024 , G06F2212/7201 , G06F2212/7203
Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.
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