Invention Grant
- Patent Title: Inspection method for wafer or DUT
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Application No.: US16192559Application Date: 2018-11-15
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Publication No.: US10679820B2Publication Date: 2020-06-09
- Inventor: Bao-Hua Niu , Jung-Hsiang Chuang , David Hung-I Su
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01J37/22
- IPC: H01J37/22 ; H01J37/16 ; H01J37/20 ; H01J37/06 ; H01J37/10 ; H01J37/244

Abstract:
A method includes applying a voltage to a wafer or a device under test (DUT). The wafer or the DUT is illuminated with an electron beam after applying the voltage to the wafer or the DUT. Cathodoluminescent light emitted from the wafer or the DUT in response to the electron beam is detected. One or more characteristics of the wafer or the DUT are determined based on the detected cathodoluminescent light.
Public/Granted literature
- US20190103248A1 INSPECTION METHOD FOR WAFER OR DUT Public/Granted day:2019-04-04
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