Invention Grant
- Patent Title: Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors
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Application No.: US16144196Application Date: 2018-09-27
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Publication No.: US10680102B2Publication Date: 2020-06-09
- Inventor: Choonghyun Lee , Kangguo Cheng , Juntao Li , Shogo Mochizuki
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/8238 ; H01L21/8234 ; H01L29/161 ; H01L29/06 ; H01L29/423 ; H01L29/04 ; H01L29/08

Abstract:
A method of forming a semiconductor device that includes forming at least two semiconductor fin structures having sidewalls with {100} crystalline planes that is present atop a supporting substrate; and epitaxially growing a source/drain region in a lateral direction from the sidewalls of each fin structure. The second source/drain regions have substantially planar sidewalls. A metal wrap around electrode is formed on an upper surface and the substantially planar sidewalls of the source/drain regions. Air gaps are formed between the source/drain regions of the at least two semiconductor fin structures.
Public/Granted literature
- US20200105928A1 REDUCTION OF TOP SOURCE/DRAIN EXTERNAL RESISTANCE AND PARASITIC CAPACITANCE IN VERTICAL TRANSISTORS Public/Granted day:2020-04-02
Information query
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