Invention Grant
- Patent Title: Methods for forming a silicon germanium tin layer and related semiconductor device structures
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Application No.: US15985261Application Date: 2018-05-21
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Publication No.: US10685834B2Publication Date: 2020-06-16
- Inventor: Nupur Bhargava , Joe Margetis , John Tolle
- Applicant: ASM IP Holding B.V.
- Applicant Address: NL Almere
- Assignee: ASM IP Holdings B.V.
- Current Assignee: ASM IP Holdings B.V.
- Current Assignee Address: NL Almere
- Agency: Snell & Wilmer L.L.P.
- Main IPC: H01L21/02
- IPC: H01L21/02 ; C23C16/40 ; C23C16/02 ; C23C16/14 ; C23C16/28 ; C23C16/455 ; C23C16/24

Abstract:
A method for forming a forming a silicon germanium tin (SiGeSn) layer is disclosed. The method may include, providing a substrate within a reaction chamber, exposing the substrate to a pre-deposition precursor pulse, which comprises tin tetrachloride (SnCl4), exposing the substrate to a deposition precursor gas mixture comprising a hydrogenated silicon source, germane (GeH4), and tin tetrachloride (SnCl4), and depositing the silicon germanium tin (SiGeSn) layer over a surface of the substrate. Semiconductor device structures including a silicon germanium tin (SiGeSn) layer formed by the methods of the disclosure are also provided.
Public/Granted literature
- US20190013199A1 METHODS FOR FORMING A SILICON GERMANIUM TIN LAYER AND RELATED SEMICONDUCTOR DEVICE STRUCTURES Public/Granted day:2019-01-10
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