Invention Grant
- Patent Title: Vertical fin field effect transistor device with reduced gate variation and reduced capacitance
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Application No.: US16029133Application Date: 2018-07-06
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Publication No.: US10707329B2Publication Date: 2020-07-07
- Inventor: Juntao Li , Kangguo Cheng , Choonghyun Lee , Shogo Mochizuki
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/08 ; H01L29/10 ; H01L21/8234 ; H01L29/78 ; H01L21/3065

Abstract:
A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin on a substrate, and depositing a sidewall liner on exposed surfaces of the vertical fin. The method further includes removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin. The method further includes laterally etching the support pillar to form a thinned support pillar, and forming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness.
Public/Granted literature
- US20200013879A1 VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICE WITH REDUCED GATE VARIATION AND REDUCED CAPACITANCE Public/Granted day:2020-01-09
Information query
IPC分类: