A master includes a transmission/reception unit which transmits/receives a signal to/from a slave, and an error detection unit which detects error occurrence by performing parity check to data received by the transmission/reception unit. Then, the error detection unit performs error detection assuming one bit of 2-bit parity included in the data received by the transmission/reception unit as even parity, and the other bit as odd parity. The present technology can be applied to a bus IF which performs communication in compliance with, for example, an I3C standard.